Figure 13.13 Example Of Dreq Input Detection In Cycle Steal Mode Edge Detection; Figure 13.14 Example Of Dreq Input Detection In Cycle Steal Mode Level Detection; Figure 13.15 Example Of Dreq Input Detection In Burst Mode Edge Detection - Renesas HD6417641 Hardware Manual
32-bit risc microcomputer superh risc engine family / sh7641 series
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CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
CKIO
Bus cycle
DREQ
DACK
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection
Section 13 Direct Memory Access Controller (DMAC)
CPU
CPU
1st acceptance
Non sensitive period
CPU
CPU
1st acceptance
Non sensitive period
CPU
CPU
1st acceptance
Non sensitive period
CPU
CPU
Non sensitive period
Burst acceptance
DMAC
CPU
2nd acceptance
Acceptance start
DMAC
CPU
2nd acceptance
Acceptance
start
DMAC
CPU
2nd acceptance
Acceptance
start
DMAC
DMAC
Rev. 4.00 Sep. 14, 2005 Page 441 of 982
REJ09B0023-0400
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