Serial Pin Select Register (Spsr); Operation In Asynchronous Mode; Figure 12.2 Data Format In Asynchronous Communication (Example With 8-Bit Data, Parity, Two Stop Bits) - Renesas H8S/2111B Hardware Manual

12.3.10 Serial Pin Select Register (SPSR)

SPSR selects the serial I/O pins. SPSR should be set before initialization. Do not set during
communication.
Bit
Bit Name
7 SPS1
6 to 0 —
Note: The program development tool (emulator) does not support SPSR.
12.4

Operation in Asynchronous Mode

Figure 12.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high
level). In asynchronous serial communication, the transmission line is usually held in the mark
state (high level). The SCI monitors the transmission line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and
receiver are independent units, enabling full-duplex communication. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer and reception.
1
Serial
0
data
Start
bit
1 bit
Figure 12.2 Data Format in Asynchronous Communication
Initial
Value R/W
0 R/W
All 0 R/W
LSB
D0 D1 D2 D3
Transmit/receive data
7 or 8 bits
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity, Two Stop Bits)
Description
Serial Port Select
Selects the serial I/O pins.
0: P86/SCK1, P85/RxD1, P84/TxD1
1: P52/ExSCK1, P51/ExRxD1, P50/ExTxD1
Reserved
The initial value should not be changed.
MSB
D4 D5 D6 D7
Idle state
(mark state)
1
0/1 1 1
Parity Stop bit
bit
1 bit or 1 or 2 bits
none
Rev. 1.00, 05/04, page 249 of 544