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14.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.13 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, SCI3 operates as described below.
1.
SCI3 performs internal initialization synchronous with a synchronization clock input or
output, starts receiving data.
2.
SCI3 stores the receive data in RSR.
3.
If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4.
If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
data
RDRF
OER
LSI
RXI interrupt
operation
request
generated
User
processing
Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.14 shows a sample flow
chart for serial data reception.
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Bit 7
Bit 0
1 frame
RDRF flag
cleared
to 0
RDR data read
Bit 7
Bit 0
Bit 1
RXI interrupt request generated
Bit 6
Bit 7
1 frame
ERI interrupt request
generated by
overrun error
RDR data has
Overrun error
not been read
processing
(RDRF = 1)
Rev. 1.00, 11/03, page 211 of 376
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