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M16C/64C Group
20.3.2
Compare Mode
In compare mode, time data
When a match is detected, the following occur:
•
Compare interrupt request
Refer to 20.4 "Interrupts" for details.
•
RTCOUT pin output level inversion
When the TOENA bit in the RTCCR1 register is 1 (compare output enabled), if a compare match is
detected, the RTCOUT pin output level is inverted.
Notes:
1. Bits for time data are as follows:
Bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register
Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register
Bits HR11 to HR10 and HR03 to HR00 in the RTCHR register
The RTCPM bit in the RTCCR1 register
2. Bits for compare data are as follows:
Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register
Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN register
Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in the RTCCHR register
The PMCMP bit in the RTCCHR register
In compare mode, set the SEIE, MNIE, or HRIE bit in the RTCCR2 register to 1 (interrupt enabled)
according to compare data (second, minute, or hour). Refer to 20.2.6 "Real-Time Clock Control
Register 2 (RTCCR2)" for details.
Compare mode has three modes: compare mode 1, compare mode 2, and compare mode 3. Operation
after a compare match differs depending on the compare mode.
•
Compare mode 1
The time data is used continuously and counting continues.
•
Compare mode 2
The reset value is used as the time data and counting continues.
•
Compare mode 3
The reset value is used as the time data and counting stops.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
(1)
(2)
and compare data
are compared, and a compare match is detected.
20. Real-Time Clock
Page 386 of 807
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