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M16C/29 Group
10. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to "1" (reset). Once this bit is set to "1", it cannot be
set to "0" (watchdog timer interrupt) in a program. Refer to "5.3 Watchdog Timer Reset" for the details of
watchdog timer reset.
When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock,the WDC
register's the WDC7 bit value for prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU
clock, the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be
calculated as given below. The period of watchdog timer is, however, subject to an error due to the
prescaler.
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period =
With sub-clock chosen for CPU clock
Watchdog timer period =
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and when erase/program operation is executing in EW1 mode without
erasesuspend required, the watchdog timer and prescaler are stopped. Counting is resumed from the held
value when the modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related
registers.
10.1 Count source protective mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer
can be kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit of PRCR register to "1" (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit of PM1 register to "1" (reset when the watchdog timer underflows).
(3) Set the PM22 bit of PM2 register to "1" (on-chip oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit of PRCR register to "0" (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Prescaler dividing (2) X Watchdog timer count (32768)
page 80 of 402
CPU clock
CPU clock
10. Watchdog Timer
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