Hold Signal; Bclk Output - Renesas M16C/60 Series Hardware Manual

Under development
This document is under development and its contents are subject to change.
M16C/6N5 Group
__________

(7) HOLD Signal

This signal is used to transfer control of the bus from CPU or DMAC to an external circuit. When the input
__________
on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
process finishes. The microcomputer remains in a hold state while the HOLD pin is held low, during which
__________
time the HLDA pin outputs a low-level signal.
Table 1.7.4 shows the microcomputer status in the hold state.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence (refer to
"Figure 1.7.5 Bus-using Priorities"). However, if the CPU is accessing an odd address in word units, the
DMAC cannot gain control of the bus during two separate accesses.
Figure 1.7.5 Bus-using Priorities
Table 1.7.4 Microcomputer Status in Hold State
BCLK
______
A to A , D to D , CS
0 19 0 15
I/O ports
__________
HLDA
Internal peripheral circuits
ALE signal
Note 1: When I/O port function is selected.
Note 2: The watchdog timer does not stop when the PM22 bit in the PM2 register is set to "1" (the count
source for the watchdog timer is the ring oscillator clock).

(8) BCLK Output

If the PM07 bit in the PM0 register is set to "0" (output enable), a clock with the same frequency as that
of the CPU clock is output as BCLK from the BCLK pin. Refer to "CPU Clock and Peripheral Function
Clock".
Table 1.7.5 shows the pin functions for each processor mode.
Rev.1.00 2003.05.30 page 36
__________
__________
HOLD > DMAC > CPU
Item
______ ______ _________ _________ _______ ________
to CS , RD, WRL, WRH, WR, BHE High-impedance
0 3
P0, P1, P3, P4 (Note 1) High-impedance
P6 to P10
__________
Status
Output
Maintains status when hold signal is received
Output "L"
ON (but watchdog timer stops (Note 2))
Undefined
Bus Control