Figure 7.2 Example Of Signal Timing In Dual Address Mode; Figure 7.3 Operations In Dual Address Mode - Renesas H8SX/1520 Series Hardware Manual

Figure 7.2 shows an example of the signal timing in dual address mode and figure 7.3 shows the
operation in dual address mode.
Address T
Address B
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Bφ
Address bus
RD
WR
TEND

Figure 7.2 Example of Signal Timing in Dual Address Mode

A
A

Figure 7.3 Operations in Dual Address Mode

DMA read cycle DMA write cycle
DSAR DDAR
Transfer
Address update setting is as follows:
Source address increment
Fixed destination address
Rev. 3.00 Mar. 14, 2006 Page 159 of 804
Section 7 DMA Controller (DMAC)
Address T
REJ09B0104-0300
B