Reception In Clock-Synchronous Serial I/O Mode - Renesas M16C Series User Manual

M30240 Group

2.4.2.3 Reception in clock-synchronous serial I/O mode

For receiving data in clock-synchronous serial I/O mode, select functions from those listed in Table 2.16
An example using the indicated options is described below. Figure 2.51 shows the operation timing, and
Figure 2.52 and Figure 2.53 show the set-up procedures.
Table 2.16: Serial I/O reception in clock synchronous serial I/O mode functions
Item
Transfer clock source
O
O
RTS function
O
CLK polarity
O
Transfer clock
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
selected, the CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disabled bit to "0".
Note 2: UART2 only.
Operation
(1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to "1", and
the transmit enable bit to "1", makes the data receivable status ready. At this time, the output from the
RTSi pin goes to "L" level, which informs the transmission side that the data receivable status is ready
(output the transfer clock from the IC on the transmission side after checking that the RTS output has
gone to "L" level).
(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi pin is
stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting right the con-
tent of the UARTi reception data in synchronization with the rising edges of the transfer clock.
(3) When 1-byte of data fills the UARTi receive register, the content of the UARTi receive register is
transmitted to the UARTi receive buffer register. The transfer clock stops at "H" level. At this time, the
receive complete flag and the UARTi receive interrupt request bit go to "1".
(4) The receive complete flag goes to "0" when the lower-order byte of the UARTi buffer register is
read.
Rev.1.00 Sep 24, 2003 Page 194 of 360
Set-up
Internal clock (f1/f8/f32)
External clcok (CLKi pin)
RTS function enabled
RTS function disabled
Input reception data at the rising
edge of the transfer clock
Input reception data at the falling
edge of the transfer clock
LSB first
MSB first
Clock-Synchronous Serial I/O
Item
O
Continuous receive
mode
O
Output transfer clock to
multiple pins (Note 1)
O
Data logic select function
(Note 2)
O
TxD, RxD I/O polarity
reverse bit (Note 2)
Set-up
Disabled
Enabled
Not selected
Selected
No reverse
Reverse
No reverse
Reverse