On-Chip Program And Storable Area For Program Data - Renesas H8SX/1500 Series Hardware Manual

Memory MAT switching is enabled by setting FMATS. However note that access to a memory
MAT is not allowed until memory MAT switching is completed. During memory MAT switching,
the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt
vector is read is undetermined. Perform memory MAT switching in accordance with the
description in section 17.11, Switching between User MAT and User Boot MAT.
Except for memory MAT switching, the erasing procedure is the same as that in user program
mode.
The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT,
and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program
Data.
17.8.4

On-Chip Program and Storable Area for Program Data

In the descriptions in this manual, the on-chip programs and program data storage areas are
assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory
which is not to be programmed or erased as long as the following conditions are satisfied.
• The on-chip program is downloaded to and executed in the on-chip RAM specified by
FTDAR. Therefore, this on-chip RAM area is not available for use.
• Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack
area.
• Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip
RAM because it will require switching of the memory MATs.
• In an operating mode in which the external address space is not accessible, such as single-chip
mode, the required procedure programs, NMI handling vector table, and NMI handling routine
should be transferred to the on-chip RAM before programming/erasing starts (download result
is determined).
• The flash memory is not accessible during programming/erasing. Programming/erasing is
executed by the program downloaded to the on-chip RAM. Therefore, the procedure program
that initiates operation, the NMI handling vector table, and the NMI handling routine should be
stored in the on-chip RAM other than the flash memory.
• After programming/erasing starts, access to the flash memory should be inhibited until FKEY
is cleared. The reset input state (period of RES = 0) must be set to at least 100 µs when the
operating mode is changed and the reset start executed on completion of programming/erasing.
Transitions to the reset state are inhibited during programming/erasing. When the reset signal
is input, a reset input state (period of RES = 0) of at least 100 µs is needed before the reset
signal is released.
Section 17 Flash Memory (0.18-(m F-ZTAT Version)
Rev. 3.00 Mar. 14, 2006 Page 617 of 804
REJ09B0104-0300