Renesas SuperH RISC SH7040 Series Manuals

Manuals and User Guides for Renesas SuperH RISC SH7040 Series. We have 2 Renesas SuperH RISC SH7040 Series manuals available for free PDF download: Hardware Manual, Supplementary Information

Renesas SuperH RISC SH7040 Series Hardware Manual (923 pages)

32-Bit RISC Microcomputer, engine, CPU Core SH-2

Brand: Renesas | Category: Computer Hardware | Size: 4.49 MB

Table of Contents

23
- Specifications
  7
- Section 1 SH7040 Series Overview
  39
- SH7040 Series Overview
  39
  - SH7040 Series Features
    39
- Block Diagram
  49
- Pin Arrangement and Pin Functions
  51
  - Pin Arrangment
    51
  - Pin Arrangement by Mode
    54
  - Pin Functions
    75
- The F-ZTAT Version Onboard Programming
  80
- Section 2 CPU
  83
- Register Configuration
  83
  - General Registers (Rn)
    83
  - Control Registers
    84
  - System Registers
    85
  - Initial Values of Registers
    85
- Data Formats
  86
  - Data Format in Registers
    86
  - Data Format in Memory
    86
  - Immediate Data Format
    86
- Instruction Features
  87
  - RISC-Type Instruction Set
    87
  - Addressing Modes
    90
  - Instruction Format
    94
- Instruction Set by Classification
  97
- Processing States
  110
  - State Transitions
    110
  - Power-Down State
    112
- Section 3 Operating Modes
  115
- Operating Modes, Types, and Selection
  115
- Explanation of Operating Modes
  116
- Pin Configuration
  117
- Clock Pulse Generator (CPG)
  119
- Overview
  119
  - Block Diagram
    119
- Oscillator
  119
  - Connecting a Crystal Oscillator
    119
  - External Clock Input Method
    120
- Prescaler
  121
- Oscillator Halt Function
  121
- Usage Notes
  121
  - Oscillator Usage Notes
    121
  - Notes on Board Design
    122
  - Spread Spectrum Clock Generator Usage Notes
    123
- Section 5 Exception Processing
  125
- Overview
  125
- Resets
  128
  - Power-On Reset
    129
  - Manual Reset
    129
- Address Errors
  130
  - Address Error Exception Processing
    131
- Interrupts
  131
  - Interrupt Priority Level
    132
  - Interrupt Exception Processing
    132
- Exceptions Triggered by Instructions
  132
  - Trap Instructions
    133
  - Illegal Slot Instructions
    133
  - General Illegal Instructions
    134
- When Exception Sources Are Not Accepted
  134
  - Immediately after a Delayed Branch Instruction
    134
  - Immediately after an Interrupt-Disabled Instruction
    134
- Stack Status after Exception Processing Ends
  135
- Notes on Use
  136
- Interrupt Controller (INTC)
  137
- Overview
  137
  - Features
    137
  - Block Diagram
    137
  - Pin Configuration
    139
  - Register Configuration
    139
- Interrupt Sources
  140
  - NMI Interrupts
    140
  - User Break Interrupt
    140
  - IRQ Interrupts
    140
  - On-Chip Peripheral Module Interrupts
    141
  - Interrupt Exception Vectors and Priority Rankings
    141
- Description of Registers
  146
- Interrupt Operation
  150
  - Interrupt Sequence
    150
  - Stack after Interrupt Exception Processing
    152
- Interrupt Response Time
  152
- Data Transfer with Interrupt Request Signals
  154
- User Break Controller (UBC)
  157
- Overview
  157
  - Features
    157
  - Block Diagram
    157
  - Register Configuration
    158
- Register Descriptions
  159
- Operation
  164
- Use Examples
  166
  - Break on CPU Instruction Fetch Cycle
    166
  - Break on CPU Data Access Cycle
    167
  - Break on DMA/DTC Cycle
    168
- Cautions on Use
  168
- Data Transfer Controller (DTC)
  171
- Overview
  171
  - Features
    171
  - Block Diagram
    172
  - Register Configuration
    173
- Register Description
  173
- Operation
  181
  - Overview of Operation
    181
  - Activating Sources
    183
  - DTC Vector Table
    183
  - Register Information Placement
    186
  - Normal Mode
    187
  - Repeat Mode
    187
  - Block Transfer Mode
    188
  - Operation Timing
    189
  - DTC Execution State Counts
    189
  - DTC Usage Procedure
    191
  - DTC Use Example
    191
- Cautions on Use
  192
- Cache Memory (CAC)
  193
- Overview
  193
  - Features
    193
  - Block Diagram
    194
  - Register Configuration
    194
- Register Explanation
  195
  - Cache Control Register CCR
    195
- Address Array and Data Array
  196
  - Cache Address Array Read/Write Space
    197
  - Cache Data Array Read/Write Space
    197
- Cautions on Use
  198
- Section 10 Bus State Controller (BSC)
  201
- Overview
  201
  - Features
    201
  - Block Diagram
    202
  - Pin Configuration
    203
  - Register Configuration
    204
  - Address Map
    205
- Description of Registers
  207
- Accessing Ordinary Space
  223
  - Basic Timing
    223
  - Wait State Control
    224
  - CS Assert Period Extension
    226
- DRAM Access
  227
  - DRAM Direct Connection
    227
  - Basic Timing
    228
  - Wait State Control
    229
  - Burst Operation
    233
  - Refresh Timing
    235
- Address/Data Multiplex I/O Space Access
  237
  - Basic Timing
    237
  - Wait State Control
    238
  - CS Assertion Extension
    239
- Waits between Access Cycles
  239
  - Prevention of Data Bus Conflicts
    239
  - Simplification of Bus Cycle Start Detection
    241
- Bus Arbitration
  241
- Memory Connection Examples
  243
- On-Chip Peripheral I/O Register Access
  248
- CPU Operation When Program Is in External Memory
  249
- Section 11 Direct Memory Access Controller (DMAC)
  251
- Overview
  251
  - Features
    251
  - Block Diagram
    253
  - Pin Configuration
    254
  - Register Configuration
    255
- Register Descriptions
  256
- Operation
  266
  - DMA Transfer Flow
    266
  - DMA Transfer Requests
    268
  - Channel Priority
    270
  - DMA Transfer Types
    273
  - Address Modes
    273
  - Dual Address Mode
    275
  - Bus Modes
    282
  - Relationship between Request Modes and Bus Modes by DMA Transfer Category
    283
  - Bus Mode and Channel Priority Order
    284
  - 11.3.10 Number of Bus Cycle States and DREQ Pin Sample Timing
    284
  - 11.3.11 Source Address Reload Function
    301
  - 11.3.12 DMA Transfer Ending Conditions
    302
  - 11.3.13 DMAC Access from CPU
    303
- Examples of Use
  303
- Cautions on Use
  310
- Section 12 Multifunction Timer Pulse Unit (MTU)
  311
- Overview
  311
  - Features
    311
  - Block Diagram
    314
  - Pin Configuration
    316
  - Register Configuration
    318
- MTU Register Descriptions
  321
  - Timer Control Register (TCR)
    321
  - Timer Mode Register (TMDR)
    326
  - Timer I/O Control Register (TIOR)
    328
  - Timer Interrupt Enable Register (TIER)
    344
  - Timer Status Register (TSR)
    347
  - Timer Counters (TCNT)
    350
  - Timer General Register (TGR)
    351
  - Timer Start Register (TSTR)
    351
  - Timer Synchro Register (TSYR)
    352
  - Timer Output Master Enable Register (TOER)
    353
  - Timer Output Control Register (TOCR)
    355
  - Timer Gate Control Register (TGCR)
    356
  - Timer Subcounter (TCNTS)
    358
  - Timer Dead Time Data Register (TDDR)
    359
  - Timer Period Data Register (TCDR)
    359
  - Timer Period Buffer Register (TCBR)
    360
- Bus Master Interface
  360
  - 16-Bit Registers
    360
  - 8-Bit Registers
    361
- Operation
  362
  - Overview
    362
  - Basic Functions
    363
  - Synchronous Operation
    368
  - Buffer Operation
    371
  - Cascade Connection Mode
    374
  - PWM Mode
    375
  - Phase Counting Mode
    379
  - Reset-Synchronized PWM Mode
    386
  - Complementary PWM Mode
    390
- Interrupts
  415
  - Interrupt Sources and Priority Ranking
    415
  - DTC/DMAC Activation
    417
  - A/D Converter Activation
    417
- Operation Timing
  418
  - Input/Output Timing
    418
  - Interrupt Signal Timing
    423
- Notes and Precautions
  427
- MTU Output Pin Initialization
  449
- Port Output Enable (POE)
  481
  - Features
    481
  - Block Diagram
    482
  - Pin Configuration
    483
  - Register Configuration
    483
- POE Register Descriptions
  484
  - Input Level Control/Status Register (ICSR)
    484
  - Output Level Control/Status Register (OCSR)
    487
- Operation
  489
  - 12.11.1 Input Level Detection Operation
    489
  - 12.11.2 Output-Level Compare Operation
    490
  - 12.11.3 Release from High-Impedance State
    490
  - 12.11.4 POE Timing
    491
  - 12.11.5 Usage Notes
    491
- Overview
  493
  - Features
    493
  - Block Diagram
    494
  - Pin Configuration
    494
  - Register Configuration
    495
- Section 13 Watchdog Timer (WDT)
  493
- Register Descriptions
  495
  - Timer Counter (TCNT)
    495
  - Timer Control/Status Register (TCSR)
    496
  - Reset Control/Status Register (RSTCSR)
    498
  - Register Access
    499
- Operation
  500
- Notes on Use
  504
- Section 14 Serial Communication Interface (SCI)
  507
- Overview
  507
  - Features
    507
  - Block Diagram
    508
  - Pin Configuration
    509
  - Register Configuration
    509
- Register Descriptions
  510
  - Receive Shift Register (RSR)
    510
  - Receive Data Register (RDR)
    510
  - Transmit Shift Register (TSR)
    510
  - Transmit Data Register (TDR)
    511
  - Serial Mode Register (SMR)
    511
  - Serial Control Register (SCR)
    514
  - Serial Status Register (SSR)
    517
  - Bit Rate Register (BRR)
    521
- Operation
  539
  - Overview
    539
  - Operation in Asynchronous Mode
    541
  - Multiprocessor Communication
    551
  - Clock Synchronous Operation
    559
- SCI Interrupt Sources and the DMAC/DTC
  570
- Notes on Use
  571
- Section 15 High Speed A/D Converter (Excluding a Mask)
  575
- Overview
  575
  - Features
    575
  - Block Diagram
    576
  - Pin Configuration
    576
  - Register Configuration
    577
- Register Descriptions
  578
- Bus Master Interface
  583
- Operation
  586
  - Select-Single Mode
    586
  - Select-Scan Mode
    587
  - Group-Single Mode
    588
  - Group-Scan Mode
    589
  - Buffer Operation
    590
  - Simultaneous Sampling Operation
    593
  - Conversion Start Modes
    595
  - Conversion Start by External Input
    598
  - A/D Conversion Time
    599
- Interrupts
  600
- Notes on Use
  601
- Section 16 MID-Speed A/D Converter (a Mask)
  605
- Overview
  605
  - Features
    605
  - Block Diagram
    606
  - Pin Configuration
    607
  - Register Configuration
    608
- Register Descriptions
  609
- Interface with CPU
  613
- Operation
  614
  - Single Mode (SCAN=0)
    614
  - Scan Mode (SCAN=1)
    616
  - Input Sampling and A/D Conversion Time
    618
  - External Trigger Input Timing
    619
- Interrupt and DMA, DTC Transfer Requests
  620
- A/D Conversion Precision Definitions
  621
- Usage Notes
  622
  - Analog Voltage Settings
    622
  - Handling of Analog Input Pins
    622
- Section 17 Compare Match Timer (CMT)
  625
- Overview
  625
  - Features
    625
  - Block Diagram
    625
  - Register Configuration
    627
- Register Descriptions
  628
- Operation
  631
  - Period Count Operation
    631
  - CMCNT Count Timing
    632
- Interrupts
  632
- Notes on Use
  634
- Section 18 Pin Function Controller
  637
- Overview
  637
- Register Configuration
  645
- Register Descriptions
  646
- Cautions on Use
  683
- Section 19 I/O Ports (I/O)
  685
- Overview
  685
- Port a
  685
  - Register Configuration
    688
  - Port a Data Register H (PADRH)
    688
  - Port a Data Register L (PADRL)
    689
- Port B
  690
  - Register Configuration
    690
  - Port B Data Register (PBDR)
    691
- Port C
  692
  - Register Configuration
    692
  - Port C Data Register (PCDR)
    693
- Port D
  694
  - Register Configuration
    696
  - Port D Data Register H (PDDRH)
    697
  - Port D Data Register L (PDDRL)
    698
- Port E
  699
  - Register Configuration
    699
  - Port E Data Register (PEDR)
    700
- Port F
  701
  - Register Configuration
    701
  - Port F Data Register PFDR
    701
- Section 20 64/128/256Kb Mask ROM
  703
- Overview
  703
- Section 21 128Kb PROM
  707
- Overview
  707
- PROM Mode
  708
  - PROM Mode Settings
    708
  - Socket Adapter Pin Correspondence and Memory Map
    708
- PROM Programming
  712
  - Programming Mode Selection
    712
  - Write/Verify and Electrical Characteristics
    713
  - Cautions on Writing
    717
  - Post-Write Reliability
    718
- Section 22 256Kb Flash Memory (F-ZTAT)
  719
- Features
  719
- Overview
  720
  - Block Diagram
    720
  - Mode Transition Diagram
    721
  - Onboard Program Mode
    722
  - User Program Mode
    723
  - Flash Memory Emulation in RAM
    724
  - Differences between Boot Mode and User Program Mode
    725
  - Block Configuration
    726
- Pin Configuration
  727
- Register Configuration
  727
- Description of Registers
  728
- On-Board Programming Mode
  736
  - Boot Mode
    737
  - User Program Mode
    741
- Programming/Erasing Flash Memory
  742
- Protection
  756
  - Hardware Protection
    756
  - Software Protection
    757
  - Error Protection
    758
- Flash Memory Emulation in RAM
  760
- Note on Flash Memory Programming/Erasing
  762
- Flash Memory Programmer Mode
  762
  - 22.11.1 Socket Adapter Pin Correspondence Diagrams
    763
  - 22.11.2 Programmer Mode Operation
    766
  - 22.11.3 Memory Read Mode
    767
  - 22.11.4 Auto-Program Mode
    771
  - 22.11.5 Auto-Erase Mode
    773
  - 22.11.6 Status Read Mode
    774
    
    Min Max Unit
    774
  - 22.11.7 Status Polling
    775
  - 22.11.8 Programmer Mode Transition Time
    776
  - 22.11.9 Cautions Concerning Memory Programming
    777
- Section 23 RAM
  779
- Overview
  779
- Operation
  779
- Section 24 Power-Down State
  781
- Overview
  781
  - Power-Down States
    781
  - Related Register
    782
- Standby Control Register (SBYCR)
  782
- Sleep Mode
  783
  - Transition to Sleep Mode
    783
  - Canceling Sleep Mode
    783
- Standby Mode
  783
  - Transition to Standby Mode
    783
  - Canceling the Standby Mode
    785
  - Standby Mode Application Example
    786
- Section 25 Electrical Characteristics (5V, 28.7 Mhz Version)
  787
- Absolute Maximum Ratings
  787
- DC Characteristics
  788
AC Characteristics/Clock Timing

790
- AC Characteristics
  790
  - Clock Timing
    790
  - Control Signal Timing
    792
  - Bus Timing
    795
  - Direct Memory Access Controller Timing
    806
  - Multifunction Timer Pulse Unit Timing
    808
  - I/O Port Timing
    809
  - Watchdog Timer Timing
    810
  - Serial Communication Interface Timing
    811
  - High-Speed A/D Converter Timing (Excluding a Mask)
    812
  - MID-Speed Converter Timing (a Mask)
    814
  - 25.3.11 Measuring Conditions for AC Characteristics
    816
- 10%, Av
  
  792
- Ta = -20 to +75° C)
  
  795
- 10%, Av
  
  796
- AV SS = 0 V, Ta = -20 to +75° C)
  
  809
- Min Typ Max
  
  812
- AC Characteristics
  
  822
- Clock Timing
  
  822
- To AV CC
  
  838
- VCC ± 10%, Av
  
  844
- Appendix A On-Chip Supporting Module Registers
  
  851
- Appendix B Block Diagrams
  
  864
- Appendix C Pin States
  
  903
- Appendix D Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions
  
  913
- Appendix E Product Code Lineup
  
  914
- Appendix F Package Dimensions
  
  916

Renesas SuperH RISC SH7040 Series Supplementary Information (27 pages)

Renesas Microcomputer Development Environment System

Brand: Renesas | Category: Computer Hardware | Size: 0.16 MB

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Renesas SuperH RISC SH7040 Series Manuals

Renesas SuperH RISC SH7040 Series Hardware Manual (923 pages)

Table of Contents

Table of Contents

AC Characteristics/Clock Timing

10%, Av

Ta = -20 to +75° C)

10%, Av

AV SS = 0 V, Ta = -20 to +75° C)

Min Typ Max

AC Characteristics

Clock Timing

To AV CC

VCC ± 10%, Av

Appendix A On-Chip Supporting Module Registers

Appendix B Block Diagrams

Appendix C Pin States

Appendix D Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions

Appendix E Product Code Lineup

Appendix F Package Dimensions

Renesas SuperH RISC SH7040 Series Supplementary Information (27 pages)

Table of Contents

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