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3.4.4 External memory area
Access to the external memory area is made using the VDCSZ7 to VDCSZ0 signals assigned to each bank (see
4.2 Memory Banks).
The "programmable peripheral I/O area", which is independent of the peripheral I/O area, is also assigned to this
area (see 4.4 Programmable Peripheral I/O Area Selection Function).
Caution ROM, RAM, and peripheral I/O areas cannot be accessed as external memory areas.
3.5 Peripheral I/O Registers
(1) Only the lower 12 bits of a 32-bit address are used for register address decoding, after being allocated to the 4
KB area of xxxxx000H to xxxxxFFFH.
(2) The lowest bit of the address is not decoded. Therefore, when the register of an odd address (2n + 1 address) is
byte-accessed, the register of an even address (2n) will be accessed.
(3) Although word-accessible registers do not exist in the NU85E, halfword access using the lower and higher bits
(in that order and ignoring the lowest 2) of a word area can be made twice to enable word access.
(4) When byte-accessible registers are halfword-accessed, the higher 8 bits become undefined in a read operation,
and the lower 8 bits of data are written to a register in a write operation.
(5) Registers other than those that control the NU85E are incorporated in each macro (MEMC, instruction/data
cache).
CHAPTER 3 CPU
Preliminary User's Manual A14874EJ3V0UM
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