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Low-power timer (LPTIM) applied to STM32L4Rxxx and STM32L4Sxxx only
41.7.10
LPTIM2 option register (LPTIM2_OR)
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 OR_1: Option register bit 1
0:
LPTIM2 input 1 is connected to I/O
1:
LPTIM2 input 1 is connected to COMP2_OUT
Bit 0 OR_0: Option register bit 0
0:
LPTIM2 input 1 is connected to I/O
1:
LPTIM2 input 1 is connected to COMP1_OUT
Note:
When both OR_1 and OR_0 are set, LPTIM2 input 1 is connected to (COMP1_OUT OR
COMP2_OUT).
1500/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0432
17
16
Res.
Res.
1
0
OR_1
OR_0
rw
rw
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