Flash Memory Control Register 0 (Fmr0) - Renesas M16C/64A Series User Manual

M16C/64A Group
9.2.1

Flash Memory Control Register 0 (FMR0)

Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
FMR01 (CPU rewrite mode select bit) (b1)
Commands can be accepted by setting the FMR01 bit to 1 (CPU rewrite mode enabled).
To set the FMR01 bit to 1, write 0 and then 1 in succession. Do not generate any interrupts or DMA
transfers between setting 0 and 1.
Change the FMR01 bit when the PM24 bit in the PM2 register is 0 ( NMI interrupt disabled) or high is
input to the NMI pin.
While in EW0 mode, write to this bit from a program in an area other than flash memory.
Enter read array mode, and then set this bit to 0.
FMSTP (Flash memory stop bit) (b3)
The FMSTP bit resets the flash memory control circuits and minimizes current consumption in the flash
memory. Access to the internal flash memory is disabled when the FMSTP bit is set to 1 (flash memory
operation stopped). Set the FMSTP bit by a program located in an area other than the flash memory.
Set the FMSTP bit to 1 under the following condition:
•
A flash memory access error occurs while erasing or programming in EW0 mode (the FMR00 bit
does not revert to 1 (ready)).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
FMR0
Bit Symbol Bit Name
FMR00 RY/BY status flag
CPU rewrite mode select
FMR01
bit
FMR02 Lock bit disable select bit
FMSTP Flash memory stop bit
—
Reserved bit
(b4)
—
Reserved bit
(b5)
FMR06
Program status flag
FMR07 Erase status flag
Address
0000 0001b (other than user boot mode)
0220h
0010 0001b (user boot mode)
Function
0 : Busy (being written or erased)
1 : Ready
0 : CPU rewrite mode disabled
1 : CPU rewrite mode enabled
0 : Lock bit enabled
1 : Lock bit disabled
0 : Flash memory operation enabled
1 : Flash memory operation stopped
(low power-mode, flash memory initialized)
Set to 0
Set to 0 in other than user boot mode
Set to 1 in user boot mode
0 : Completed as expected
1 : Completed in error
0 : Completed as expected
1 : Completed in error
9. Power Control
Reset Value
RW
RO
RW
RW
RW
RW
RW
RO
RO
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