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5.2.5
IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ
to IRQ
5
Bit
7
—
Initial value
0
Read/Write
R/W
Reserved bits
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0—IRQ
to IRQ
5
interrupts IRQ
to IRQ
5
sensing.
Bits 5 to 0:
IRQ5SC to IRQ0SC
0
1
.
0
6
5
—
IRQ5SC
0
0
R/W
R/W
Sense Control (IRQ5SC to IRQ0SC): These bits select whether
0
are requested by level sensing of pins IRQ
0
Description
Interrupts are requested when IRQ
Interrupts are requested by falling-edge input at IRQ
4
3
IRQ4SC
IRQ3SC
IRQ2SC
0
0
R/W
R/W
IRQ to IRQ sense control
5
0
These bits select level sensing or falling-edge
sensing for IRQ to IRQ interrupts
5
5
to IRQ
inputs are low
5
0
Rev. 3.00 Mar 21, 2006 page 91 of 814
Section 5 Interrupt Controller
2
1
0
IRQ1SC
IRQ0SC
0
0
0
R/W
R/W
R/W
0
to IRQ
, or by falling-edge
0
(Initial value)
to IRQ
5
0
REJ09B0302-0300
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