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M16C/29 Group
7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)
When main clock stop is detected when the CM20 bit is "1" (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to "SFR",
"Reset").
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During
main clock stop, do not set the CM20 bit to "1" and the CM27 bit to "0".)
7.8.2 Operation When CM27 bit = 1 (Oscillation Stop and Re-oscillation Detect Interrupt)
When the main clock corresponds to the CPU clock source and the CM20 bit is "1" (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock comes
to a halt:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the CPU clock and
clock
source for peripheral functions in place of the main clock.
• CM21 bit = 1 (on-chip oscillator clock for CPU clock source)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
When the PLL clock corresponds to the CPU clock source and the CM20 bit is "1", the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to "1"
(on-chip oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
When the CM20 bit is "1", the system is placed in the following state if the main clock re-oscillates from the
stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
page 58 of 402
7. Clock Generation Circuit
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