Input/Output Functional Description - Samsung M391B5273DH0 Hardware User Manual

Unbuffered DIMM

7. Input/Output Functional Description

Symbol Type
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive
CK0-CK1
SSTL edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of
CK0-CK1
crossing)
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
CKE0-CKE1 SSTL
initiates the Power Down mode, or the Self-Refresh mode
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
S0-S1 SSTL command decoder is disabled, new command are ignored but previous operations continue. This signal provides for
external rank selection on systems with multiple ranks.
RAS, CAS, WE SSTL RAS, CAS, and WE (ALONG WITH S) define the command being entered.
When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming the function is enabled in the
ODT0-ODT1 SSTL
Extended Mode Register Set (EMRS).
V
Supply Reference voltage for SSTL 15 I/O inputs.
REFDQ
V
Supply Reference voltage for SSTL 15 command/address inputs.
REFCA
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered
V
Supply
DDQ
DIMM designs, V
BA0-BA2 SSTL Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the column address, In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a pre-
A0-A14 SSTL
charge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used
to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-the-fly) will be performed (HIGH, no burst chop; Low, burst chopped).
DQ0-DQ63
SSTL Data and Check Bit Input/Output pins.
CB0-CB7
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
1
SSTL during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
DM0-DM8
the DQ and DQS loading.
Power and ground for DDR3 SDRAM input buffers, and core logic. V
V ,V
Supply
DD SS
these modules.
1
DQS0-DQS8
SSTL Data strobe for input and output data.
1
DQS0-DQS8
These signals and tied at the system planar to either V
SA0-SA2 -
range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected
SDA -
from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL
SCL -
bus time to V
Power supply for SPD EEPROM. This supply is separate from the V
V
Supply
DDSPD
from 3.0V to 3.6V.
RESET - The RESET pin is connected to the RESET pin on each DRAM. When low, all DRAMs are set to a know state.
This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee
EVENT Output
the electrical level requirement is met for the EVENT pin on TS/SPD part
NOTE :
1. DM8, DQS8 and DQS8 are for ECC UDIMM only.
datasheet
shares the same power plane as V
DDQ
to act as a pull-up on the system board.
DDSPD
to act as a pull-up on the system board.
DDSPD
- 7 -
Function
pins.
DD
and V pins are tied to V
DD DDQ
or V to configure the serial SPD EERPOM address
SS DDSPD
/V power plane. EEPROM supply is operable
DD DDQ
Rev. 1.0
DDR3L SDRAM
/V planes on
DD DDQ