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Unbuffered DIMM
1. DDR3L Unbuffered DIMM Ordering Information
2
Part Number
M391B5773DH0-YF8/H9/K0
M391B5273DH0-YF8/H9/K0
NOTE :
1. "##" - F8/H9/K0
2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11
- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
DDR3-800
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
• V
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
DDQ
• 400MHz f
for 800Mb/sec/pin, 533MHz f
CK
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10,11
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• Burst Length: 8 (Interleave without any limit, sequential with starting address "000" only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
• Asynchronous Reset
3. Address Configuration
Organization
256Mx8(2Gb) based Module
datasheet
Density
Organization
2GB
4GB
DDR3-1066
6-6-6
7-7-7
2.5
1.875
6
7
15
13.125
15
13.125
37.5
37.5
52.5
50.625
for 1066Mb/sec/pin, 667MHz f
CK
85°C, 3.9us at 85°C < T
CASE
Row Address
A0-A14
Component Composition
256Mx64
256Mx8(K4B2G0846D-HY##)*9
512Mx72
256Mx8(K4B2G0846D-HY##)*18
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
for 1333Mb/sec/pin, 800MHz f
CK
≤ 95°C
CASE
Column Address
A0-A9
- 4 -
DDR3L SDRAM
Number of
Rank
1
2
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
for 1600Mb/sec/pin
CK
Bank Address
Auto Precharge
BA0-BA2
A10/AP
Rev. 1.0
Height
30mm
30mm
Unit
ns
nCK
ns
ns
ns
ns
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