Table 8.4 Available Output Signals And Settings In Each Port - Renesas H8SX/1520 Series Hardware Manual

Table 8.4
Output
Specification
Port Signal Name
P1 6 SCK3_OE
0 TxD3_OE
P2 3 TIOCD3_OE*
2 TIOCC3_OE*
1 SCS2_OE
TIOCA3_OE*
0 TIOCB3_OE*
P3 7 TIOCB2_OE*
PO15_OE*
6 TIOCA2_OE*
PO14_OE*
5 TIOCB1_OE*
PO13_OE*
4 TIOCA1_OE*
PO12_OE*
3 TIOCD0_OE*
PO11_OE*
2 TIOCC0_OE*
PO10_OE*
1 TIOCB0_OE*
PO9_OE*
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Available Output Signals and Settings in Each Port
Output
Signal
Name
SCK3
TxD3
TIOCD3
TIOCC3
SCS2
TIOCA3
TIOCB3
TIOCB2
PO15
TIOCA2
PO14
TIOCB1
PO13
TIOCA1
PO12
TIOCD0
PO11
TIOCC0
PO10
TIOCB0
PO9
Signal
Selection
Register
Settings Peripheral Module Settings
When SCMR_3.SMIF = 1:
SCR_3.TE = 1 or SCR_3.RE = 1
while SMR_3.GM = 0, SCR.CKE [1, 0] = 01 or
while SMR.GM = 1
When SCMR_3.SMIF = 0:
SCR_3.TE = 1 or SCR_3.RE = 1
while SMR_3.C/A = 0, SCR_3.CKE [1, 0] = 01 or
while SMR_3.C/A = 1, SCR_3.CKE 1 = 0
SCR.TE = 1
TPU.TMDR.BFB = 0, TPU.TIORL_3.IOD3 = 0,
TPU.TIORL_3.IOD[1,0] = 01/10/11
TPU.TMDR.BFA = 0, TPU.TIORL_3.IOC3 = 0,
TPU.TIORL_3.IOD[1,0] = 01/10/11
SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 0, or
SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 1
while SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1
TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] =
01/10/11
TPU.TIORH_3.IOB3 = 0, TPU.TIORH_3.IOB[1,0] =
01/10/11
TPU.TIOR_2.IOB3 = 0, TPU.TIOR_2.IOB[1,0] = 01/10/11
NDERH.NDER15 = 1
TPU.TIOR_2.IOA3 = 0, TPU.TIOR_2.IOA[1,0] = 01/10/11
NDERH.NDER14 = 1
TPU.TIOR_1.IOB3 = 0, TPU.TIOR_1.IOB[1,0] = 01/10/11
NDERH.NDER13 = 1
TPU.TIOR_1.IOA3 = 0, TPU.TIOR_1.IOA[1,0] = 01/10/11
NDERH.NDER12 = 1
TPU.TMDR_0.BFB = 0, TPU.TIORL_0.IOD3 = 0,
TPU.TIORL_0.IOD[1,0] = 01/10/11
NDERH.NDER11 = 1
TPU.TMDR_0.BFA = 0, TPU.TIORL_0.IOC3 = 0,
TPU.TIORL_0.IOD[1,0] = 01/10/11
NDERH.NDER10 = 1
TPU.TIORH_0.IOB3 = 0, TPU.TIORH_0.IOB[1,0] =
01/10/11
NDERH.NDER9 = 1
Section 8 I/O Ports
Rev. 3.00 Mar. 14, 2006 Page 239 of 804
REJ09B0104-0300