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Number
8.5.5
Updating Code And Memory Region Attributes............................................8-24
8.6
Data Cache Operation.........................................................................................8-24
8.6.1
Data Cache Load Hit ......................................................................................8-25
8.6.2
Data Cache Read Miss....................................................................................8-25
8.6.3
Write-Through Mode......................................................................................8-26
8.6.3.1
Data Cache Store Hit in Write-Through Mode ..........................................8-26
8.6.3.2
Data Cache Store Miss in Write-Through Mode........................................8-26
8.6.4
Write-Back Mode ...........................................................................................8-26
8.6.4.1
Data Cache Store Hit in Write-Back Mode................................................8-26
8.6.4.2
Data Cache Store Miss in Write-Back Mode .............................................8-27
8.6.5
Data Accesses to Caching-Inhibited Memory Regions..................................8-27
8.6.6
Atomic Memory References...........................................................................8-28
8.7
Cache Initialization after Reset...........................................................................8-29
8.8
Debug Support....................................................................................................8-29
8.8.1
Instruction and Data Cache Operation in Debug Mode .................................8-29
8.8.2
Instruction and Data Cache Operation with a Software Monitor Debugger ..8-30
9.1
Features.................................................................................................................9-1
9.2
PowerPC Architecture Compliance......................................................................9-2
9.3
Address Translation..............................................................................................9-3
9.3.1
Translation Disabled.........................................................................................9-3
9.3.2
Translation Enabled..........................................................................................9-3
9.3.3
TLB Operation..................................................................................................9-5
9.4
Using Access Protection Groups ..........................................................................9-6
9.5
Protection Resolution Modes................................................................................9-7
9.6
Memory Attributes ...............................................................................................9-8
9.7
Translation Table Structure ..................................................................................9-9
9.7.1
Level-One Descriptor .....................................................................................9-13
9.7.2
Level-Two Descriptor ....................................................................................9-14
9.8
Programming Model...........................................................................................9-14
9.8.1
IMMU Control Register (MI_CTR)...............................................................9-16
9.8.2
DMMU Control Register (MD_CTR)............................................................9-17
9.8.3
IMMU/DMMU Effective Page Number Register (Mx_EPN) .......................9-18
9.8.4
IMMU Tablewalk Control Register (MI_TWC)............................................9-18
9.8.5
DMMU Tablewalk Control Register (MD_TWC).........................................9-19
9.8.6
IMMU Real Page Number Register (MI_RPN).............................................9-20
9.8.7
DMMU Real Page Number Register (MD_RPN)..........................................9-22
9.8.8
MMU Tablewalk Base Register (M_TWB) ...................................................9-23
9.8.9
MMU Current Address Space ID Register (M_CASID) ...............................9-23
x
CONTENTS
Title
Chapter 9
Memory Management Unit (MMU)
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA
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