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Paragraph
Number
16.3.5
8-, 16-, and 32Bit Port Size Configuration.....................................................16-7
16.3.6
Parity Configuration .......................................................................................16-8
16.3.7
Memory Bank Protection Status.....................................................................16-8
16.3.8
UPM-Specific Registers .................................................................................16-8
16.3.9
GPCM-Specific Registers ..............................................................................16-8
16.4
Register Descriptions..........................................................................................16-8
16.4.1
Base Registers (BRx) .....................................................................................16-8
16.4.2
Option Registers (ORx)................................................................................16-10
16.4.3
Memory Status Register (MSTAT) ..............................................................16-13
16.4.4
Machine A Mode Register/Machine B Mode Registers (MxMR) ...............16-13
16.4.5
Memory Command Register (MCR)............................................................16-15
16.4.6
Memory Data Register (MDR).....................................................................16-16
16.4.7
Memory Address Register (MAR) ...............................................................16-17
16.4.8
Memory Periodic Timer Prescaler Register (MPTPR) ................................16-17
16.5
General-Purpose Chip-Select Machine (GPCM) .............................................16-18
16.5.1
Timing Configuration...................................................................................16-18
16.5.1.1
Chip-Select Assertion Timing ..................................................................16-19
16.5.1.2
Chip-Select and Write Enable Deassertion Timing .................................16-20
16.5.1.3
Relaxed Timing ........................................................................................16-22
16.5.1.4
Output Enable (OE) Timing .....................................................................16-25
16.5.1.5
Programmable Wait State Configuration .................................................16-25
16.5.1.6
Extended Hold Time on Read Accesses...................................................16-25
16.5.2
Boot Chip-Select Operation .........................................................................16-27
16.5.3
External Asynchronous Master Support.......................................................16-28
16.5.4
Special Case: Bursting with External Transfer Acknowledge: ....................16-29
16.6
User-Programmable Machines (UPMs) ...........................................................16-30
16.6.1
Requests........................................................................................................16-31
16.6.1.1
Internal/External Memory Access Requests ............................................16-31
16.6.1.2
UPM Periodic Timer Requests.................................................................16-32
16.6.1.3
Software RequestsÑMCR run Command ...............................................16-32
16.6.1.4
Exception Requests ..................................................................................16-32
16.6.2
Programming the UPM.................................................................................16-33
16.6.3
Clock Timing................................................................................................16-33
16.6.4
The RAM Array ...........................................................................................16-35
16.6.4.1
RAM Words .............................................................................................16-36
16.6.4.2
Chip-Select Signals (CxTx)......................................................................16-39
16.6.4.3
Byte-Select Signals (BxTx)......................................................................16-39
16.6.4.4
General-Purpose Signals (GxTx, GOx)....................................................16-40
16.6.4.5
Loop Control (LOOP) ..............................................................................16-42
16.6.4.6
Exception Pattern Entry (EXEN) .............................................................16-43
16.6.4.7
Address Multiplexing (AMX) ..................................................................16-43
16.6.4.8
Transfer Acknowledge and Data Sample Control (UTA, DLT3) ............16-47
16.6.4.9
Disable Timer Mechanism (TODT) .........................................................16-48
xvi
CONTENTS
Title
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA
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