Functional Description Of Display Controller; Brief Description Of The Sub-Block; Data Flow - Samsung S5PC110 Manual

S5PC110_UM 1 0BDISPLAY CONTROLLER

1.3 FUNCTIONAL DESCRIPTION OF DISPLAY CONTROLLER

1.3.1 BRIEF DESCRIPTION OF THE SUB-BLOCK

The display controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator.
To configure the display controller, the VSFR has 121 programmable register sets, one gamma LUT register set
(64 registers), one i80 command register set (12 registers), and five 256x32 palette memories.
VDMA is a dedicated display DMA that transfers video data in frame memory to VPRCS. By using this special
DMA, you can display video data on screen without CPU intervention.
VPRCS receives video data from VDMA and sends it to display device (LCD) through data ports (RGB_VD, or
SYS_VD), after changing the video data into a suitable data format. For example, 8-bit per pixel mode (8 bpp
mode) or 16-bit per pixel mode (16 bpp mode).
VTIME consists of programmable logic to support the variable requirement of interface timing and rates commonly
found in different LCD drivers. The VTIME block generates RGB_VSYNC, RGB_HSYNC, RGB_VCLK,
RGB_VDEN, VEN_VSYNC, VEN_HSYNC, VEN_FIELD, VEN_HREF and SYS_CS0, SYS_CS1, SYS_WE, and
so on.
Using the display controller data, you can select one of the above data paths by setting
DISPLAY_PATH_SEL[1:0] (0xE010_7008). For more information, refer to Chapter, "02.03.S5PC110_CMU".

1.3.2 DATA FLOW

FIFO is in the VDMA. If FIFO is empty or partially empty, the VDMA requests data fetching from frame memory
based on burst memory transfer mode. The data transfer rate determines the size of FIFO.
The display controller contains five FIFOs (three local FIFOs and two DMA FIFOs), since it needs to support the
overlay window display mode. Use one FIFO for one screen display mode.
VPRCS fetches data from FIFO. It contains the following functions for final image data: blending, image
enhancing, and scheduling. It also supports the overlay function. This can overlay any image up to five window
images, whose smaller or same size can be blended with the main window image having programmable alpha
blending or color (chroma) key function.
shows the data flow from system bus to output buffer.
Figure 1-2
VDMA has five DMA channels (Ch0 ~ Ch4)and three local input interfaces (CAMIF0, CAMIF1, and CAMIF2). The
Color Space Conversion (CSC) block changes Hue (YCbCr, local input only) data to RGB data for blending
operation. Also, the alpha values written in SFR determine the level of blending. Data from output buffer appears
in the Video Data Port.
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