Bank Onenand Type Selection Register; Smc Status Register - Samsung S3C2416 User Manual

S3C2416X RISC MICROPROCESSOR
4.7

BANK ONENAND TYPE SELECTION REGISTER

Register
SMBONETYPER
BANK5TYPE
BANK4TYPE
BANK3TYPE
BANK2TYPE
BANK1TYPE
NOTE: Type of bank0 OneNAND is determined by OM[4:2] signals (See table 1-4).
4.8

SMC STATUS REGISTER

Register
SMCSR
WaitStatus
Address R/W
0x4F000100 R/W
Bit
[31:6] Read undefined.
[5] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
[4] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
[3] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
[2] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
[1] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
[0] Reserved
Address R/W
0x4F000200 R
Bit
[31:1] Read undefined.
[0] External wait status, read:
0 = nWAIT deasserted.
1 = nWAIT asserted.
After an externally waited transfer that was terminated early,
this bit value can detect when
nWAIT is deasserted. At all other times, this bit reads zero.
Description
SMC Bank OneNAND type selection
register
Description
Description
SMC status register
Description
STATIC MEMORY CONTROLLER
Reset Value
0x0
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reset Value
0x0
Initial State
0x0
0x0
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