Onenand Controller - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

7. OneNAND Controller

Overview
S5PV210 supports external 16-bit bus for OneNAND and Flex-OneNAND memory devices. The OneNAND controller
supports asynchronous and synchronous read/write bus operations. It also integrates its own dedicated DMA engine
and microsequencer to accelerate the OneNAND memory device operation.
7.1. Signal Description
Signal
Xm0ADDR[15:0]
Xm0DATA[15:0]
ONANDXL_CSn[1:0]
Xm0WEn
Xm0OEn
ONDXL_INT[0:1]
ONDXL_AVD
ONDXL_RPn
ONDXL_SMCLK
PmOndCEB
I/O
Xm0ADDR[15:0] (ADDR Bus) outputs address during
memory read/write address phase, inputs data during
IO
memory read data phase and outputs data during
memory write data phase.
Xm0DATA[15:0] (Data Bus) outputs address during
memory read/write address phase, inputs data during
IO
memory read data phase and outputs data during
memory write data phase.
ONANDXL_CSn[0:1] (Chip Select) are activated when
the address of a memory is within the address region of
each bank. ONANDXL_CSn[0:1] can be assigned to
O
either SROMC or OneNAND controller by System
Controller SFR setting.
Active LOW.
Xm0WEn (Write Enable) indicates that the current bus
cycle is a write cycle.
O
Active LOW.
Xm0OEn (Output Enable) indicates that the current bus
cycle is a read cycle.
O
Active LOW.
I Interrupt inputs from OneNAND memory Bank 0, 1.
Address valid output.
O
Active LOW.
System reset output for OneNAND memory.
O
Active LOW.
Static memory clock for synchronous static memory
devices.
O
Must be less than 83MHz.
OneNand memory signal. Should be connected to c110
I
chip select signal externally.
Description Comment
ONANDXL_CSn[0] should be
connected to OneNand device
externally.
- ONDXL_INT[0] is connected to
OneNand device internally.
- 4.7Kohm external pull-up
90