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S3C2501X
5.4 BUS INTERFACE SIGNALS
The bus interface signals transfer information between the S3C2501X and external memory device.
These divide into address and data which used commonly, SDRAM interface signals for SDRAM and memory
device interface for ROM/SRAM, etc.
For detail description for the bus interface signals, refer to the table below.
Signal Name
ADDR
DATA
B0SIZE
nOE
nRCS
nEWAIT/nREADY
HCLKO
CKE
nSDCS
nSDRAS
nSDCAS
nWBE/nBE/DQM
nSDWE/nWE16
XBMREQ
XBMACK
NOTES:
1.
O = Output from the S3C2501X.
2.
I = Input to the S3C2501X.
3.
B = Bi-direction.
Table 5-2. Bus Interface Signals
Pins
Active
24
HIGH
32
HIGH
2
HIGH
1
LOW
8
LOW
1
LOW
1
HIGH
1
HIGH
2
LOW
1
LOW
1
LOW
4
LOW
1
LOW
1
HIGH
1
HIGH
I/O
O
Specifies the physical address of the external device
B
Specifies data of the external device
I
Specifies data bus access size for the Bank 0
O
Specifies read/write state from S3C2501X. When
S3C2501X read from ext I/O device, nOE's value is
1'b0.
O
Specifies which ext I/O device is selected.
I
Signal be controlled from ext I/O slow device to delay
cycles in data read and write.
O
S3C2501X system clock out
O
Clock enable for SDRAM
O
Chip select strobe for SDRAM
O
Row address strobe for SDRAM
O
Column address strobe for SDRAM
O
Write byte enable
O
Write enable for ROM, SRAM, Flash that have 16bit-
data width and SDRAM.
I
External Master bus request
O
External bus acknowledge
MEMORY CONTROLLER
Description
5-5
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