Figure 9.2 Block Diagram Of Tpu (Unit 1) - Renesas H8SX/1500 Series Hardware Manual

Input/output pins
Channel 9: TIOCA9
TIOCB9
TIOCC9
TIOCD9
Channel 10: TIOCA10
TIOCB10
Channel 11: TIOCA11
TIOCB11
Clock input
Internal clock:
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
External clock:
TCLKE
TCLKF
TCLKG
TCLKH
Input/output pins
Channel 6: TIOCA6
TIOCB6
TIOCC6
TIOCD6
Channel 7: TIOCA7
TIOCB7
Channel 8: TIOCA8
TIOCB8
[Legend]
TSTRB: Timer start register
TSYRB: Timer synchronous register
TCR: Timer control register
TMDR: Timer mode register
TIOR (H, L): Timer I/O control registers (H, L)

Figure 9.2 Block Diagram of TPU (Unit 1)

TIER: Timer interrupt enable register
TSR: Timer status register
TGR (A, B, C, D): Timer general registers (A, B, C, D)
TCNT: Timer counter
Rev. 3.00 Mar. 14, 2006 Page 257 of 804
Section 9 16-Bit Timer Pulse Unit (TPU)
Interrupt request signals
Channel 9:
Channel 10:
Channel 11:
Internal data bus
Interrupt request signals
Channel 6:
Channel 7:
Channel 8:
REJ09B0104-0300
TGI9A
TGI9B
TGI9C
TGI9D
TCI9V
TGI10A
TGI10B
TCI10V
TCI10U
TGI11A
TGI11B
TCI11V
TCI11U
TGI6A
TGI6B
TGI6C
TGI6D
TCI6V
TGI7A
TGI7B
TCI7V
TCI7U
TGI8A
TGI8B
TCI8V
TCI8U