Figure 17.18 Address Map Of Overlaid Ram Area - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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Figure 17.18 shows an example of overlaying flash memory block area EB0.

The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in

RAMER from among the eight blocks, EB0 to EB7, of the user MAT.

To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in

RAMER to 1 and bits RAM2 to RAM0 to B'000.

For programming/erasing the user MAT, the procedure programs including a download program

of the on-chip program must be executed. At this time, the download area should be specified so

that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area

in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the

tuned data must be saved in an unused area beforehand.

Figure 17.19 shows an example of the procedure to program the tuned data in block EB0 of the

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Flash memory

Figure 17.18 Address Map of Overlaid RAM Area

Section 17 Flash Memory (0.18-(m F-ZTAT Version)

This area can be accessed via

both the on-chip RAM and flash

memory area.

Rev. 3.00 Mar. 14, 2006 Page 627 of 804

REJ09B0104-0300

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