Section 2 Cpu - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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Section 2 CPU

• Two base registers

 Vector base register

 Short address base register

• 4-Gbyte address space

 Program: 4 Gbytes

• High-speed operation

 All frequently-used instructions executed in one or two states

 8/16/32-bit register-register add/subtract: 1 state

 8 × 8-bit register-register multiply:

 16 ÷ 8-bit register-register divide:

 16 × 16-bit register-register multiply:

 32 ÷ 16-bit register-register divide:

 32 × 32-bit register-register multiply:

 32 ÷ 32-bit register-register divide:

• Four CPU operating modes

 Normal mode

 Middle mode

 Advanced mode

 Maximum mode

• Power-down modes

 Transition is made by execution of SLEEP instruction

 Choice of CPU operating clocks

Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1520

Group. Normal, middle, and maximum modes are not supported.

2. The multiplier and divider are supported by the H8SX/1520 Group.

3. In the H8SX/1520 Group, an instruction is fetched in 32-bit mode.

Rev. 3.00 Mar. 14, 2006 Page 20 of 804

REJ09B0104-0300

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