Exception Sources And Exception Handling Vector Table; Table 4.2 Exception Handling Vector Table - Renesas H8SX/1500 Series Hardware Manual

Section 4 Exception Handling
4.2

Exception Sources and Exception Handling Vector Table

Different vector table address offsets are assigned to different exception sources. The vector table
addresses are calculated from the contents of the vector base register (VBR) and vector table
address offset of the vector number. The start address of the exception service routine is fetched
from the exception handling vector table indicated by this vector table address.
Table 4.2 shows the correspondence between the exception sources and vector table address
offsets. Table 4.3 shows the calculation method of exception handling vector table addresses.
Since the usable modes differ depending on the product, for details on the available modes, see
section 3, MCU Operating Modes.
Table 4.2 Exception Handling Vector Table
Exception Source
Reset
Reserved for system use
Illegal instruction
Trace
Reserved for system use
Interrupt (NMI)
Trap instruction (#0)
(#1)
(#2)
(#3)
CPU address error
3
DMA address error*
Reserved for system use
Rev. 3.00 Mar. 14, 2006 Page 74 of 804
REJ09B0104-0300
Vector Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14

63
Vector Table Address Offset*
2
Normal Mode*
H'0000 to H'0001
H'0002 to H'0003
H'0004 to H'0005
H'0006 to H'0007
H'0008 to H'0009
H'000A to H'000B
H'000C to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
H'0018 to H'0019
H'001A to H'001B
H'001C to H'001D

H'007E to H'007F
1
Advanced, Middle,
Maximum Modes
H'0000 to H'0003
H'0004 to H'0007
H'0008 to H'000B
H'000C to H'000F
H'0010 to H'0013
H'0014 to H'0017
H'0018 to H'001B
H'001C to H'001F
H'0020 to H'0023
H'0024 to H'0027
H'0028 to H'002B
H'002C to H'002F
H'0030 to H'0033
H'0034 to H'0037
H'0038 to H'003B

H'00FC to H'00FF