Figure 12.16 Example Of Operation For Transmission In Clocked Synchronous Mode; Figure 12.17 Sample Serial Transmission Flowchart - Renesas H8SX/1500 Series Hardware Manual

Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated

Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode

Initialization
Start transmission
Read TDRE flag in SSR
TDRE = 1
Write transmit data to TDR and
clear TDRE flag in SSR to 0
All data transmitted
Read TEND flag in SSR
TEND = 1
Clear TE bit in SCR to 0
<End>

Figure 12.17 Sample Serial Transmission Flowchart

Transfer direction
Bit 0 Bit 1
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
1 frame
[1]
[2]
No
Yes
No
[3]
Yes
No
Yes
Section 12 Serial Communication Interface (SCI)
Bit 7 Bit 0 Bit 1
TXI interrupt
request generated
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI state check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0. However, the TDRE
flag is checked and cleared
automatically when the DMAC is
initiated by a transmit data empty
interrupt (TXI) request and writes data
to TDR.
Rev. 3.00 Mar. 14, 2006 Page 425 of 804
Bit 6 Bit 7
TEI interrupt request
generated
REJ09B0104-0300