Dma Module Request Select Register (Dmrsr); Transfer Modes; Table 7.3 Transfer Modes - Renesas H8SX/1520 Series Hardware Manual

7.2.8

DMA Module Request Select Register (DMRSR)

DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source.
The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no
interrupt source. For the vector numbers of the interrupt sources, refer to table 7.4.
Bit
Bit Name
Initial Value
R/W
7.3

Transfer Modes

Table 7.3 shows the DMAC transfer modes. The transfer modes can be specified to the individual
channels.
Table 7.3
Address
Mode Transfer mode
•
Dual
address
•
•
Repeat or block size
= 1 to 65,536 bytes,
1 to 65,536 words, or
1 to 65,536
longwords
•
Single
address
•
•
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7 6
0 0
R/W R/W
Transfer Modes
Activation Source
•
Normal transfer
Repeat transfer
Block transfer
•
•
Instead of specifying the source or destination address
registers, data is directly transferred from/to the external
device using the DACK pin
The same settings as above are available other than address
register setting (e.g., above transfer modes can be specified)
One transfer can be performed in one bus cycle (the types of
transfer modes are the same as those of dual address modes)
5 4
0 0
R/W R/W R/W
Common Function
•
Auto request
(activated by
CPU)
On-chip module
•
interrupt
•
External request
Section 7 DMA Controller (DMAC)
3 2 1
0 0 0
R/W R/W
Address Register
Source
DSAR
Total transfer
size: 1 to 4
Gbytes or not
specified
Offset addition
Extended repeat
area function
DSAR/
DACK
Rev. 3.00 Mar. 14, 2006 Page 157 of 804
0
0
R/W
Destina-
tion
DDAR
DACK/
DDAR
REJ09B0104-0300