Figure 9.17 Example Of Buffer Operation (2) - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer

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Section 9 16-Bit Timer Pulse Unit (TPU)

(b) When TGR is an input capture register

Figure 9.17 shows an operation example in which TGRA has been designated as an input capture

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges

have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of

input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.

Rev. 3.00 Mar. 14, 2006 Page 310 of 804

REJ09B0104-0300

Figure 9.17 Example of Buffer Operation (2)

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