Figure 17.7 Automatic-Bit-Rate Adjustment Operation; Table 17.6 System Clock Frequency For Automatic-Bit-Rate Adjustment - Renesas H8SX/1500 Series Hardware Manual

Section 17 Flash Memory (0.18-(m F-ZTAT Version)
(1)
Serial Interface Setting by Host
The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data,
one stop bit, and no parity.
When a transition to boot mode is made, the boot program embedded in this LSI is initiated.
When the boot program is initiated, this LSI measures the low period of asynchronous serial
communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and
adjusts the bit rate of the SCI_4 to match that of the host.
When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit
adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1
byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The
bit rate may not be adjusted within the allowable range depending on the combination of the bit
rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the
host and the system clock frequency of this LSI must be as shown in table 17.6.
Start
bit

Figure 17.7 Automatic-Bit-Rate Adjustment Operation

Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment

Bit Rate of Host System Clock Frequency of This LSI External Clock Frequency
9,600 bps 8 to 18 MHz
19,200 bps 16 to 18 MHz
Rev. 3.00 Mar. 14, 2006 Page 600 of 804
REJ09B0104-0300
D0 D1 D2
Measure low period (9 bits) (data is H'00)
D3 D4 D5 D6
4 to 9 MHz
8 to 9 MHz
Stop bit
D7
High period of
at least 1 bit