Dma Address Control Register (Dacr) - Renesas H8SX/1520 Series Hardware Manual

7.2.7

DMA Address Control Register (DACR)

DACR specifies the operating mode and transfer method.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
31 AMS
30 DIRS
29 to 27 
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31 30
AMS DIRS
0 0
R/W R/W
23 22
— — SAT1
0 0
R R R/W
15 14
SARIE —
0 0
R/W R
7 6
DARIE —
0 0
R/W R
Initial
Value R/W
0 R/W
0 R/W
0 R/W
29 28 27
— — —
0 0 0
R R R
21 20 19
SAT0 —
0 0 0
R/W R
13 12 11
— SARA4 SARA3
0 0 0
R R/W R/W
5 4 3
— DARA4 DARA3
0 0 0
R R/W R/W
Description
Address Mode Select
Selects address mode from single or dual address
mode. In single address mode, the DACK pin is enabled
according to the DACKE bit.
0: Dual address mode
1: Single address mode
Single Address Direction Select
Specifies the data transfer direction in single address
mode. This bit s ignored in dual address mode.
0: Specifies DSAR as source address
1: Specifies DDAR as destination address
Reserved
These are read-only bits and cannot be modified.
Section 7 DMA Controller (DMAC)
26 25
RPTIE ARS1
0 0
R/W R/W
18 17
— DAT1
0 0
R R/W
10 9
SARA2 SARA1
0 0
R/W R/W
2 1
DARA2 DARA1
0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 151 of 804
REJ09B0104-0300
24
ARS0
0
R/W
16
DAT0
0
R/W
8
SARA0
0
R/W
0
DARA0
0
R/W