Figure 21.10 Tpu Input/Output Timing; Figure 21.11 Tpu Clock Input Timing; Figure 21.12 Ppg Output Timing; Figure 21.13 Sck Clock Input/Output Timing - Renesas H8SX/1520 Series Hardware Manual

Section 21 Electrical Characteristics
Pφ
TCLKA to TCLKD*
TCLKE to TCLKH
Note:
Rev. 3.00 Mar. 14, 2006 Page 772 of 804
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Pφ
Output compare
1
output*
Input capture
1
input*
Notes: 1. TIOCA0 to TIOCA3*
2
TIOCD0* , TIOCD3*
TIOCC6, TIOCC9, TIOCD6, and TIOCD9
2. Supported only by the H8SX/1527.

Figure 21.10 TPU Input/Output Timing

* Supported only by the H8SX/1527.

Figure 21.11 TPU Clock Input Timing

Pφ
PO15 to PO8

Figure 21.12 PPG Output Timing

SCK3, SCK4

Figure 21.13 SCK Clock Input/Output Timing

t
TOCD
2 2
, TIOCB0 to TIOCB3* , TIOCC0*
2
, TIOCA6 to TIOCA11, TIOCB6 to TIOCB11,
t
TCKS
t
TCKWL
t
POD
t
t t
SCKW SCKr SCKf
t
Scyc
t
TICS
2 2
, TIOCC3* ,
t
TCKS
t
TCKWH