Relationship Between Data Input/Output Pins And Shift Register; Figure 14.3 Relationship Between Data Input/Output Pins And The Shift Register - Renesas H8SX/1520 Series Hardware Manual

14.4.3

Relationship between Data Input/Output Pins and Shift Register

The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 14.3
show the relationship.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 14.3 (1)). The SSU
transmits serial data from the SSI pin and receives serial data from the SSO pin when operating
with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 14.3 (2)).
The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode
when operating with BIDE = 1 (bidirectional mode) (see figures 14.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function
as an input pin when MSS = 0 (see figures 14.3 (5) and (6)).
(1) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 1, TE = 1, and RE = 1
Shift register
(4) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 1, and either TE or RE = 1
(5) When SSUMS = 1 and MSS = 1
Shift register

Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register

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(SSTRSR)
Shift register
(SSTRSR)
(SSTRSR)
Section 14 Synchronous Serial Communication Unit (SSU)
(2) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 0, TE = 1, and RE = 1
SSCK
SSO Shift register
(SSTRSR)
SSI
(3) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 0, and either TE or RE = 1
SSCK
Shift register
SSO
(SSTRSR)
SSI
(6) When SSUMS = 1 and MSS = 0
SSCK
Shift register
SSO
(SSTRSR)
SSI
Rev. 3.00 Mar. 14, 2006 Page 527 of 804
SSCK
SSO
SSI
SSCK
SSO
SSI
SSCK
SSO
SSI
REJ09B0104-0300