Figure 13.1 Hcan Block Diagram - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer
Hide thumbs Also See for H8SX/1500 Series:
Table of Contents

Advertisement

Section 13 Controller Area Network (HCAN)
• Support for various modes
 Hardware reset
 Software reset
 Normal status (error-active, error-passive)
 Bus off status
 HCAN configuration mode
 HCAN sleep mode
 HCAN halt mode
• Other features
 DMAC can be activated by message reception mailbox (HCAN mailbox 0 only)
• Module stop mode can be set
MBI
Message buffer
Mailboxes
Message control, message data,
MC0 to MC15, MD0 to MD15
MPI
Microprocessor interface
CPU interface
Control register
Status register
• Message Buffer Interface (MBI)
The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN
transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU.
For receive messages, the data received by the CDLC is stored automatically.
• Microprocessor Interface (MPI)
The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN
internal data, status, and so forth.
• CAN Data Link Controller (CDLC)
The CDLC, conforming to the Bosch CAN Ver. 2.0B active standard, performs transmission
and reception of messages (data frames, remote frames, error frames, overload frames, inter-
frame spacing), as well as CRC checking, bus arbitration, and other functions.
Rev. 3.00 Mar. 14, 2006 Page 450 of 804
REJ09B0104-0300
HCAN

Figure 13.1 HCAN Block Diagram

(CDLC)
Data Link Controller
Bosch CAN 2.0B active
LAFM
CAN
HTxD
Tx buffer
HRxD
Rx buffer

Advertisement

Table of Contents
loading

Table of Contents