Master Control Register (Mcr) - Renesas H8SX/1520 Series Hardware Manual

13.3.1

Master Control Register (MCR)

MCR controls the HCAN.
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
7 MCR7

6
5 MCR5

4, 3
2 MCR2
1 MCR1
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7 6
MCR7 — MCR5
0 0
R/W R
R/W
Initial
Value
0
0
0
All 0
0
0
Section 13 Controller Area Network (HCAN)
5 4 3
— —
0 0 0
R R
R/W Description
R/W HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically
exits HCAN sleep mode on detection of CAN bus
operation.
R Reserved
This is a read-only bit and cannot be modified.
R/W HCAN Sleep Mode
When this bit is set to 1, the HCAN enters HCAN
sleep mode. When this bit is cleared to 0, HCAN
sleep mode is released.
R Reserved
These are read-only bits and cannot be modified.
R/W Message Transmission Method
0: Transmission order determined by message
identifier priority
1: Transmission order determined by mailbox
(buffer) number priority (TXPR1 > TXPR15)
R/W Halt Request
When this bit is set to 1, the HCAN enters HCAN
HALT mode. When this bit is cleared to 0, HCAN
HALT mode is released.
2 1
MCR2 MCR1
0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 453 of 804
REJ09B0104-0300
0
MCR0
1
R/W