Section 14 Synchronous Serial Communication Unit (SSU)
Figure 14.1 shows a block diagram of the SSU.
SSTDR 0
SSTDR 1
SSTDR 2
SSTDR 3
SSI
[Legend]
SSCRH:
SSCRL:
SSCR2:
SSMR:
SSER:
SSSR:
SSTDR0 to SSTDR3:
SSRDR0 to SSRDR3:
SSTRSR:
Rev. 3.00 Mar. 14, 2006 Page 510 of 804
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Module data bus
SSRDR 0
SSRDR 1
SSRDR 2
SSRDR 3
SSTRSR
Selector
SSO
SS control register H
SS control register L
SS control register 2
SS mode register
SS enable register
SS status register
SS transmit data registers 0 to 3
SS receive data registers 0 to 3
SS shift register
Figure 14.1 Block Diagram of SSU
SSCRH
SSCRL
SSMR
SSER
SSSR
Control circuit
Clock
Clock
selector
SCS
SSCK (External clock)
Internal data bus
OEI
CEI
RXI
TXI
TEI
Pφ
Pφ/4
Pφ/8
Pφ/16
Pφ/32
Pφ/64
Pφ/128
Pφ/256