Mailbox Interrupt Mask Register (Mbimr) - Renesas H8SX/1500 Series Hardware Manual

Section 13 Controller Area Network (HCAN)

13.3.12 Mailbox Interrupt Mask Register (MBIMR)

MBIMR enables or disables interrupt requests by individual mailboxes.
Bit 15
Bit Name MBIMR7
Initial Value 1
R/W R/W
Bit 7
Bit Name MBIMR15
Initial Value 1
R/W R/W
Bit Bit Name
15 MBIMR7
14 MBIMR6
13 MBIMR5
12 MBIMR4
11 MBIMR3
10 MBIMR2
9 MBIMR1
8 MBIMR0
7 MBIMR15
6 MBIMR14
5 MBIMR13
4 MBIMR12
3 MBIMR11
2 MBIMR10
1 MBIMR9
0 MBIMR8
Rev. 3.00 Mar. 14, 2006 Page 470 of 804
REJ09B0104-0300
14 13
MBIMR6 MBIMR5 MBIMR4
1 1
R/W R/W
6 5
MBIMR14 MBIMR13 MBIMR12
1 1
R/W R/W
Initial
Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
12 11 10
MBIMR3 MBIMR2
1 1
R/W R/W R/W
4 3
MBIMR11 MBIMR10
1 1
R/W R/W R/W
Description
Mailbox Interrupt Mask (MBIMRx)
When MBIMRn (n = 1 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When
set to 1, the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPR
clearing caused by transmission end or
transmission cancellation. The interrupt source in
a receive mailbox is RXPR setting on reception
end.
9 8
MBIMR1 MBIMR0
1 1 1
R/W R/W
2 1 0
MBIMR9 MBIMR8
1 1 1
R/W R/W