Index - Renesas H8SX/1520 Series Hardware Manual

Numerics
0-output/1-output .................................... 302
11 consecutive recessive bits .................. 484
16-bit timer pulse unit (TPU) ................. 251
A
A/D conversion accuracy........................ 561
A/D converter ......................................... 547
Absolute accuracy................................... 561
Absolute maximum ratings..................... 761
AC characteristics................................... 764
Address error ............................................ 79
Address error exception handling ............. 80
Address map ............................................. 72
Address modes........................................ 158
All-module-clock-stop mode .. 671, 672, 680
Arbitration field .............................. 491, 495
Asynchronous mode ............................... 405
AT-cut parallel-resonance type............... 665
Available output signal and settings
in each port ............................................. 239
B
Bφ clock output control .......................... 685
Bit rate ............................................ 398, 487
Block diagram............................................. 2
Block structure........................................ 574
Block transfer mode................................ 164
Boot mode ...................................... 571, 599
Buffer segment ....................................... 487
Bus access modes ................................... 168
Bus arbitration ........................................ 131
Bus configuration ................................... 127
Bus controller (BSC) .............................. 125
Bus-released state ..................................... 64
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Index

C
CAN bus interface................................... 503
Clock....................................................... 408
Clock pulse generator ............................. 661
Clock synchronous communication
mode ....................................................... 539
Clocked synchronous mode .................... 422
Communications protocol ....................... 632
Configuration mode ................................ 484
Control field............................................ 491
Controller area network (HCAN)............ 449
CPU priority control function over
DMAC .................................................... 120
Crystal resonator ..................................... 665
Cycle stealing mode................................ 168
D
Data direction register............................. 212
Data field................................................. 491
Data frame reception............................... 496
Data register............................................ 212
DC characteristics ................................... 762
Direct convention.................................... 430
DMA controller (DMAC) ....................... 133
Double-buffered structure ....................... 405
Download pass/fail result parameter....... 588
DTC interface ......................................... 502
Dual address mode.................................. 158
E
Electrical characteristics ......................... 761
Error protection....................................... 624
Error signal ............................................. 430
Exception handling ................................... 73
Rev. 3.00 Mar. 14, 2006 Page 799 of 804
REJ09B0104-0300