Figure 14.7 Example Of Reception Operation (Ssu Mode) - Renesas H8SX/1500 Series Hardware Manual

(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
SCS
SSCK
Bit
SSI
0
RDRF
LSI operation
User operation Dummy-read SSRDR0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
SCS
SSCK
SSI
Bit
(LSB first)
0
SSI
Bit
(MSB first)
7
RDRF
LSI operation
User operation Dummy-readSSRDR0
(3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0
SCS
SSCK
SSI
Bit
(LSB first)
0
SSRDR3
SSI
Bit
(MSB first)
7
SSRDR0
RDRF
LSI operation
User operation
Dummy-readSSRDR0

Figure 14.7 Example of Reception Operation (SSU Mode)

Section 14 Synchronous Serial Communication Unit (SSU)
1 frame
Bit Bit Bit Bit Bit Bit Bit
1 2 3 4 5 6 7
SSTDR0 (LSB first transmission)
RXI interrupt
generated
1 frame
Bit Bit Bit Bit Bit Bit Bit
1 2 3 4 5 6 7
SSRDR1
Bit Bit Bit Bit Bit Bit Bit
6 5 4 3 2 1 0
SSRDR0
Bit Bit Bit Bit
to to to
7 0 7 0
SSRDR2 SSRDR1
Bit Bit Bit Bit
to to to
0 7 0 7
SSRDR1 SSRDR2
1 frame
Bit Bit Bit Bit Bit
7 6 5 4 3
SSTDR0 (MSB first transmission)
Read SSRDR0
Bit Bit Bit Bit Bit Bit Bit
0 1 2 3 4 5 6
SSRDR0
Bit Bit Bit Bit Bit Bit Bit
7 6 5 4 3 2 1
SSRDR1
RXI interrupt generated
Bit Bit Bit
to
7 0 7
SSRDR0
Bit Bit Bit
to
0 7 0
SSRDR3
RXI interrupt generated
Rev. 3.00 Mar. 14, 2006 Page 535 of 804
Bit Bit Bit
2 1 0
RXI interrupt
generated
Bit
7
Bit
0
REJ09B0104-0300