Dma Module Request Select Register (Dmrsr); Transfer Modes; Table 7.3 Transfer Modes - Renesas H8SX/1500 Series Hardware Manual

7.2.8

DMA Module Request Select Register (DMRSR)

DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source.
The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no
interrupt source. For the vector numbers of the interrupt sources, refer to table 7.4.
Bit 7
Bit Name
Initial Value 0
R/W R/W
7.3

Transfer Modes

Table 7.3 shows the DMAC transfer modes. The transfer modes can be specified to the individual
channels.
Table 7.3 Transfer Modes
Address
Mode Transfer mode
•
Dual
Normal transfer
address
•
Repeat transfer
•
Block transfer
Repeat or block size
= 1 to 65,536 bytes,
1 to 65,536 words, or
1 to 65,536
longwords
•
Single
Instead of specifying the source or destination address
address
registers, data is directly transferred from/to the external
device using the DACK pin
•
The same settings as above are available other than address
register setting (e.g., above transfer modes can be specified)
•
One transfer can be performed in one bus cycle (the types of
transfer modes are the same as those of dual address modes)
6 5
0 0
R/W R/W R/W
Activation Source
•
Auto request
(activated by
CPU)
•
On-chip module
interrupt
•
External request
Section 7 DMA Controller (DMAC)
4 3 2
0 0 0
R/W R/W
Common Function
•
Total transfer
size: 1 to 4
Gbytes or not
specified
•
Offset addition
•
Extended repeat
area function
Rev. 3.00 Mar. 14, 2006 Page 157 of 804
1 0
0 0
R/W R/W
Address Register
Destina-
Source tion
DSAR DDAR
DACK/
DSAR/
DACK
DDAR
REJ09B0104-0300