Clock; Figure 12.4 Phase Relation Between Output Clock And Transmit Data - Renesas H8SX/1520 Series Hardware Manual

Section 12 Serial Communication Interface (SCI)
12.4.3

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input to
the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4.
SCK
TxD

Figure 12.4 Phase Relation between Output Clock and Transmit Data

Rev. 3.00 Mar. 14, 2006 Page 408 of 804
REJ09B0104-0300
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0 D0 D1 D2 D3
(Asynchronous Mode)
D4 D5 D6 D7 0/1
1 frame
1 1