Interrupts; Error Counters; Register Access; Register Hold In Standby Modes - Renesas H8SX/1500 Series Hardware Manual

13.8.4

Interrupts

When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are
not set by reception completion, transmission completion, or transmission cancellation of the set
mailboxes.
13.8.5

Error Counters

In the case of error active and error passive, REC and TEC perform count up and down normally.
In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. When REC
reaches 96 during the count, IRR4 and GSR1 are set.
13.8.6

Register Access

Byte or word access can be performed for all HCAN registers. Longword access should be
avoided.
13.8.7

Register Hold in Standby Modes

All HCAN registers are initialized in hardware standby mode and software standby mode.
13.8.8

Use on Bit Manipulation Instructions

Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to
clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared.
Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 505 of 804
REJ09B0104-0300