Register Descriptions - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer

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Section 17 Flash Memory (0.18-(m F-ZTAT Version)

Register Descriptions

The flash memory has the following registers. To access these registers, the FLSHE bit in the

system control register (SYSCR) must be set to 1. For details on SYSCR, see section 3.2.2,

System Control Register (SYSCR).

Programming/Erasing Interface Registers:

• Flash code control/status register (FCCS)

• Flash program code select register (FPCS)

• Flash erase code select register (FECS)

• Flash key code register (FKEY)

• Flash MAT select register (FMATS)

• Flash transfer destination address register (FTDAR)

Programming/Erasing Interface Parameters:

• Download pass and fail result parameter (DPFR)

• Flash pass and fail result parameter (FPFR)

• Flash program/erase frequency parameter (FPEFEQ)

• Flash multipurpose address area parameter (FMPAR)

• Flash multipurpose data destination area parameter (FMPDR)

• Flash erase block select parameter (FEBS)

• RAM emulation register (RAMER)

There are several operating modes for accessing the flash memory. Respective operating modes,

registers, and parameters are assigned to the user MAT and user boot MAT. The correspondence

between operating modes and registers/parameters for use is shown in table 17.3.

Rev. 3.00 Mar. 14, 2006 Page 578 of 804

REJ09B0104-0300

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