Ss Mode Register (Ssmr) - Renesas H8SX/1520 Series Hardware Manual

14.3.3

SS Mode Register (SSMR)

SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous
serial communication.
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
7 MLS
6 CPOS
5 CPHS

4, 3
2 CKS2
1 CKS1
0 CKS0
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7 6 5
MLS CPOS CPHS
0 0 0
R/W R/W R/W
Initial
Value R/W
0 R/W
0 R/W
0 R/W
All 0 R/W
0 R/W
0 R/W
0 R/W
Section 14 Synchronous Serial Communication Unit (SSU)
4 3
— —
0 0
R/W R/W
Description
MSB First/LSB First Select
Selects that the serial data is transmitted in MSB first or
LSB first.
0: LSB first
1: MSB first
Clock Polarity Select
Selects the SSCK clock polarity.
0: High output in idle mode, and low output in active
mode
1: Low output in idle mode, and high output in active
mode
Clock Phase Select (Only for SSU Mode)
Selects the SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Clock Rate Select
Select the transfer clock rate (prescaler division rate)
when an internal clock is selected.
000: Reserved
001: Pφ/4
010: Pφ/8
011: Pφ/16
Rev. 3.00 Mar. 14, 2006 Page 517 of 804
2 1
CKS2 CKS1 CKS0
0 0
R/W R/W R/W
100: Pφ/32
101: Pφ/64
110: Pφ/128
111: Pφ/256
REJ09B0104-0300
0
0