Figure 7.35 Example Of Transfer In Single Address Mode Activated By Dreq Falling Edge - Renesas H8SX/1500 Series Hardware Manual

Activation Timing by DREQ Falling Edge
(3)
Figure 7.35 shows an example of single address mode activated by the DREQ signal falling edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the single cycle, receiving
the next transfer request resumes and then a low level of the DREQ signal is detected. This
operation is repeated until the transfer is completed.
Bφ
DREQ
Address bus
DACK
DMA
Wait
operation
Channel
[1]
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
[1]
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the
DREQ signal.
[4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 7.35 Example of Transfer in Single Address Mode Activated
Bus
released
Transfer source/
Transfer destination
Single
Duration of transfer
request disabled
Request
Min. of 3 cycles
[2] [3]
by DREQ Falling Edge
DMA single Bus
cycle released
Wait
Request
Min. of 3 cycles
[5]
[4]
Transfer request
enable resumed
Rev. 3.00 Mar. 14, 2006 Page 193 of 804
Section 7 DMA Controller (DMAC)
DMA single Bus
cycle released
Transfer source/
Transfer destination
Single
Wait
Duration of transfer
request disabled
[6] [7]
Transfer request
enable resumed
REJ09B0104-0300