Interrupt Sources; Table 13.4 Hcan Interrupt Sources - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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Interrupt Sources

Table 13.4 lists the HCAN interrupt sources. These sources can be masked except the reset

processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox

interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER).

For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller.

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Error passive interrupt (TEC ≥ 128 or REC ≥ 128)

Bus off interrupt (TEC ≥ 256)

Reset processing interrupt by power-on reset

Remote frame reception

Error warning interrupt (TEC ≥ 96)

Error warning interrupt (REC ≥ 96)

Overload frame transmission interrupt

Unread message overwrite

Detection of CAN bus operation in HCAN sleep mode

Mailbox 0 message reception

Mailbox 1-15 message reception

Message transmission/cancellation

Section 13 Controller Area Network (HCAN)

Rev. 3.00 Mar. 14, 2006 Page 501 of 804

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REJ09B0104-0300

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