Figure 7.28 Example Of Transfer In Block Transfer Mode - Renesas H8SX/1520 Series Hardware Manual

Section 7 DMA Controller (DMAC)
(3)
Block Transfer Mode
In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer
request is completed.
In figure 7.28, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer
mode.
Bφ
Address
bus
RD
LHWR,
LLWR
TEND
Bus
released
Rev. 3.00 Mar. 14, 2006 Page 186 of 804
REJ09B0104-0300
Downloaded from Elcodis.com electronic components distributor
DMA DMA DMA
read cycle write cycle read cycle
Block transfer

Figure 7.28 Example of Transfer in Block Transfer Mode

DMA DMA
write cycle read cycle
Bus
released
DMA DMA DMA
write cycle read cycle write cycle
Last block transfer cycle
Bus
released