Traces; Table 4.4 Status Of Ccr And Exr After Trace Exception Handling - Renesas H8SX/1520 Series Hardware Manual

Section 4 Exception Handling
4.4

Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit
must be cleared to 0. For details on interrupt control modes, see section 5, Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table
4.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is
canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit
saved on the stack retains its value of 1, and when control is returned from the trace exception
handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not
carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 4.4 Status of CCR and EXR after Trace Exception Handling
Interrupt Control Mode
0
2
[Legend]
1: Set to 1
0: Cleared to 0
:
Retains the previous value.
Rev. 3.00 Mar. 14, 2006 Page 78 of 804
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CCR
I UI
Trace exception handling cannot be used.

1
EXR
I2 to I0 T

0